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Formal Verification of Partial Good Self-Test Fencing Structures
2007
Formal Methods in Computer Aided Design (FMCAD'07)
The concept of applying partial fencing to logic built-in self test (LBIST) hardware structures for the purpose of using partially good chips is well known in the chip design industry. Deceptively difficult though is the task of verifying that any particular implementation of partial fencing logic actually provides the desired behavior of blocking down-stream impact of all signals from fenced interfaces, and also ensuring that the partial fencing does not inadvertently preclude any common logic
doi:10.1109/fmcad.2007.4401999
fatcat:z5s5wpclnvhp5c6wwpmsq7hree