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DESIGN AND VERIFICATION FLOW OF MULTI-STAGE SIGMA-DELTA ADC DIGITAL CORE
Issues of radio electronics
There is a need for analog-to-digital converters with high signal-to-noise ratio and large signal bandwidth to solve a number of radiolocation problems. Developing such ADC is a challenge in the analog core, digital core and verification. The design flow of the digital core must take into account the possibility of changing the analog core specification at any design stage, provide the ability to quickly obtain the synthesizable RTL code of the device and conduct its functional verification.doi:10.21778/2218-5453-2018-8-56-63 fatcat:hkrdozqjo5a67feygg2nxr6v2u