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A tutorial on logic synthesis for lookup-table based FPGAs
1992
IEEE/ACM International Conference on Computer-Aided Design
The ability to shorten development cycles has made Field-Programmable Gate Arrays (FPGAs) an attractive alternative to Standard Cells an,d Mask Programmed Gate Arrays for the realization of ASICs. One important class of FPGAs are those that use lookup tables (L UTs) to implement combinational logic. The ability of a K-input LUT to implement any Boolean function of Ii-variables di$eren,tiates the synthesis of LUT circuits from synthesis for conventional ASIC technologies. The major difference
doi:10.1109/iccad.1992.279399
dblp:conf/iccad/Francis92
fatcat:lrb3epjrzzarzoffs2bmivbukm