A tutorial on logic synthesis for lookup-table based FPGAs

Francis
1992 IEEE/ACM International Conference on Computer-Aided Design  
The ability to shorten development cycles has made Field-Programmable Gate Arrays (FPGAs) an attractive alternative to Standard Cells an,d Mask Programmed Gate Arrays for the realization of ASICs. One important class of FPGAs are those that use lookup tables (L UTs) to implement combinational logic. The ability of a K-input LUT to implement any Boolean function of Ii-variables di$eren,tiates the synthesis of LUT circuits from synthesis for conventional ASIC technologies. The major difference
more » ... urs during the technology mapping phase of logic synthesis. For values of I( greater th,an 3, th.e large number of functions that can be implemented by a K-input LUT makes it impractical to use conventional library-based technology mapping. However, the completeness of the set of functions th.at can be implemented by a LlJT eliminates the need for a library of separate junctions. In addition, this completeness can be leveraged to optimize the final circuit.
doi:10.1109/iccad.1992.279399 dblp:conf/iccad/Francis92 fatcat:lrb3epjrzzarzoffs2bmivbukm