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Identifying and predicting timing-critical instructions to boost timing speculation
2011
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture - MICRO-44 '11
Circuit-level timing speculation has been proposed as a technique to reduce dependence on design margins and eliminating power/performance overheads. Recent work has proposed microarchitectural methods to dynamically detect and recover from timing errors in processor logic. To a large extent existing work has relied on statistical error models and has not evaluated potential disparity of error rates at the level of static instructions. In this paper, we analyze gatelevel hardware models for an
doi:10.1145/2155620.2155636
dblp:conf/micro/XinJ11
fatcat:hn5pdtpbybbqbo3b3ta7tgaoji