On Designs of Radix Converters Using Arithmetic Decompositions

Y. Iguchi, T. Sasao, M. Matsuura
2006 36th International Symposium on Multiple-Valued Logic (ISMVL'06)  
In arithmetic circuits for digital signal processing, radixes other than two are often used to make circuits faster. In such cases, radix converters are necessary. However, in general, radix converters tend to be complex. This paper considers design methods for p-nary to binary converters. It introduces a new design technique called arithmetic decomposition. It also compares the amount of hardware and performance of radix converters implemented on FPGAs.
doi:10.1109/ismvl.2006.31 dblp:conf/ismvl/IguchiSM06 fatcat:owzrsi3zh5exzicvnxwl6byfsm