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A vector-pipeline DSP for low-rate videophones
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)
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We propose a vector-pipeline processor VP-DSP for lowrate videophones, which can encode and decode 10 frames/sec. of QCIF through a 29.2kbps low-rate line. We have already fabricated a VP-DSP LSI by a 0.35 m CMOS process. The area of the VP-DSP core is 4.2mm¡ . It works properly at 25MHz/1.6V with the power dissipation of 49mW. Its peak performance is up to 400MOPS, 8.2GOPS/W.
doi:10.1109/aspdac.2001.913259
fatcat:cmrk6al7pbabfggkuaecbsx6va