Decomposition of finite state machines for area, delay minimization

R.S. Shelar, M.P. Desai, H. Narayanan
Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040)  
In this paper, we consider the state assignment problem as that of the decomposition of finite state machines and transform this decomposition problem into an orthogonal partitioning problem with a certain cost function. We attempt to justify this cost function in two ways, first by using an idealized model of multi-level logic implementation, and second by empirical studies of a particular benchmark circuit. We describe a greedy algorithm to minimize this cost function. We present results
more » ... resent results obtained by running the algorithm on a set of 16 MCNC benchmarks. We compare these results with other state assignment techniques such as JEDI [6] and NOVA [5] . For multilevel implementations of the benchmark state machines, we find that the implementations obtained after using JEDI [6] were, on average, 8.52% larger in area and 81.87% slower in delay than the implementations obtained using our approach. The implementations obtained after using NOVA were, on average, 4.40% larger in area and 104.96% slower in delay when compared with implementations obtained using our approach. Our scheme has the potential to serve as an alternative to conventional state assignment tools since we observe that it produces good results for larger finite state machines.
doi:10.1109/iccd.1999.808606 dblp:conf/iccd/ShelarDN99 fatcat:huk6jues75cgdhw7y4oia2jnci