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Teaching basics of instruction pipelining with HDLDLX
2004
Proceedings of the 2004 workshop on Computer architecture education held in conjunction with the 31st International Symposium on Computer Architecture - WCAE '04
HDLDLX is a graphically described VHDL model of 5-stage integer pipeline of well known DLX processor. It can be used as a platform explaining logic-level implementation of pipelined processor as a complement to SW functional simulators. Students can interact with model by implementing hazard resolution logic or modifying the pipeline structure. Even though that the model is internally represented in VHDL, the previous knowledge of this language is not required. HDLDLX can be used in conjunction
doi:10.1145/1275571.1275593
dblp:conf/wcae/Becvar04
fatcat:3bhy4xc4arhvjg7jhtqvflqb6y