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Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors
[chapter]
2006
Lecture Notes in Computer Science
This paper presents a scalable and partitionable asynchronous bus arbiter for use with chip multiprocessors (CMP) and its corresponding pre-layout simulation results using VHDL. The arbiter exploits the advantage of a concurrency control instruction (Brk) provided by the micro-threaded microprocessor model to set the priority processor and move the circulated arbitration token at the most likely processor to issue the create instruction. This mechanism provides latency hiding during token
doi:10.1007/11682127_18
fatcat:4oy6xtikxra6dee2n5zxocjxvq