Towards design and validation of mixed-technology SOCs

S. Mir, B. Charlot, G. Nicolescu, P. Coste, F. Parrain, N. Zergainoh, B. Courtois, A. Jerraya, M. Rencz
<span title="">2000</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/cuck3arl5zcl5nv2jjpeyumj44" style="color: black;">Proceedings of the 10th Great Lakes Symposium on VLSI - GLSVLSI &#39;00</a> </i> &nbsp;
This paper illustrates an approach to design and validation of heterogeneous systems. The emphasis is placed on devices which incorporate MEMS parts in either a single mixed-technology (CMOS + micromachining) SOC device, or alternatively as a hybrid system with the MEMS part in a separate chip. The design flow is general, and it is illustrated for the case of applications embedding CMOS sensors. In particular, applications based on fingerprint recognition are considered since a rich variety of
more &raquo; ... ensors and data processing algorithms can be considered. A high level multilanguage/multi-engine approach is used for system specification and co-simulation. This also allows for an initial high-level architecture exploration, according to performance and cost requirements imposed by the target application. Thermal simulation of the overall device, including packaging, is also considered since this can have a significant impact in sensor performance. From the selected system specification, the actual architecture is finally generated via a multi-language co-design approach which can result in both hardware and software parts. The hardware parts are composed of available IP cores. For the case of a single chip implementation, the most important issue of embedded-core-based testing is briefly considered, and current techniques are adapted for testing the embedded cores in the SOC devices discussed.
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/330855.330950">doi:10.1145/330855.330950</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/glvlsi/MirCNCPZCJR00.html">dblp:conf/glvlsi/MirCNCPZCJR00</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/awxvh2hsazcfrjawmc34nj3r4y">fatcat:awxvh2hsazcfrjawmc34nj3r4y</a> </span>
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