Impact of Two-Step Recessed SiGe S/D Engineering for Advanced pMOSFETs of 32 nm Technology Node and Beyond [chapter]

N. Kusunoki, N. Yasutake, M. Awano, I. Mizushima, H. Yoshimura, S. Yamada, F. Matsuoka
Simulation of Semiconductor Processes and Devices 2007  
The two-step recessed SiGe Source/ Drain (S/D) structure, which is one of the embedded SiGe S/D engineering techniques, is a leading candidate for advanced pMOSFETs from the viewpoint of good roll-off characteristics and high channel strain. In this paper, we reveal the merits of this technology for the application to the 32 nm technology node, including the methodology for suppressing the layout effect by TCAD analysis.
doi:10.1007/978-3-211-72861-1_29 fatcat:cx4odadjrnczlea2rlqj7bklsi