A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf
.
Masking AES with $$d+1$$ Shares in Hardware
[chapter]
2016
Lecture Notes in Computer Science
Masking requires splitting sensitive variables into at least d + 1 shares to provide security against DPA attacks at order d. To this date, this minimal number has only been deployed in software implementations of cryptographic algorithms and in the linear parts of their hardware counterparts. So far there is no hardware construction that achieves this lower bound if the function is nonlinear and the underlying logic gates can glitch. In this paper, we give practical implementations of the AES
doi:10.1007/978-3-662-53140-2_10
fatcat:zyxgtv6adjhrzdvo46gi2zfsvi