Adiabatic SRAM for Low Power Devices

Amit Saxena, Kshitij Shinghal, Deepti Shinghal
2017 International Journal of Recent Trends in Electrical & Electronics Engineering  
With modernization and requirement of computational devices having facility of having communication anytime anywhere, there is an ever-increasing demand of battery operated handheld portable devices which are small in size, low cost, reliable and consumes low power. Analysis has proved that memory array consumes more 60 % power and poses maximum power constraints on hand held and portable devices. This power constraint has led to the requirement of Low power memories for such devices. The power
more » ... consumption of SRAM varies widely depending on how frequently it is accessed and some ICs can consume many watts at full bandwidth. On the other hand, static RAM used at a somewhat slower frequency, such as in applications with moderately clocked microprocessors, draws very little power and can have a nearly negligible power consumption when sitting idle in the region of a few micro-watts. Several techniques have been proposed to manage power consumption of SRAM-based memory structures. In this paper a robust adiabatic SRAM is designed. The main aim is to use adiabatic switching circuits to compensate throughput degradation, so a medium throughput for SRAM can be achieved. Proposed architecture is designed using adiabatic switching principles. Proposed adiabatic SRAM is tested using OrCAD PSPICE. The results show that performance of adiabatic SRAM is better than other contemporary SRAMs
doi:10.7323/ijrte/v4_i2/03 fatcat:7ogbiy52pbbqxeg5lr6kmmindq