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In this work we investigate the architecture of a Via Patterned Gate Array (VPGA) , focusing primarily on: 1) the optimal lookup table (LUT) size; and 2) a comparison the crossbar and switch block routing architectures. Unlike FPGAs, the routing architectures in a VPGA do not dominate the total area of the circuit. Therefore our results suggest that using smaller LUTs results in a much faster and smaller design. In the routing architecture comparison, our results also show that the switchdoi:10.1145/640000.640039 dblp:conf/ispd/PatelCSP03 fatcat:2kupn2qo5bdnpe57dbzbnscsie