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Simulation of 1.0 m CMOS Baseline Process at AEMD of Shanghai Jiao Tong University

Didi Ma, Xiaodong Wang, Yun Shen, Xiulan Cheng
2015 Proceedings of the 4th International Conference on Mechatronics, Materials, Chemistry and Computer Engineering 2015   unpublished

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A standard 1.0m CMOS process are developed at AEMD (Center for Advanced Electronic Materials and Devices), which is a public platform about advanced micro-nano fabrication. The process supports 1.0 μm twin well technology, with double poly-Si, double metal, and defines the standard process modules in the micro lab. Process and simulation data details are presented with the electrical test structure and device characterization for the first six-inch baseline run.
doi:10.2991/icmmcce-15.2015.497 fatcat:qpi2vpu5ufbwfijcak5ye2txsi
Citation

Didi Ma, Xiaodong Wang, Yun Shen, Xiulan Cheng. "Simulation of 1.0 m CMOS Baseline Process at AEMD of Shanghai Jiao Tong University." Proceedings of the 4th International Conference on Mechatronics, Materials, Chemistry and Computer Engineering 2015 (2015)