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1 FPGAs are an appealing solution for the space-based remote sensing applications. However, in a low-earth orbit, configuration bits of SRAM-based FPGAs are susceptible to single-event upsets (SEUs). In this paper, a new protected CLB and FPGA architecture are proposed which utilize error detection and correction codes to correct SEUs occurred in LUTs of the FPGA. The fault detection and correction is achieved using online or offline fast detection and correction cycles. In the latter,doi:10.1109/ipdps.2007.370378 dblp:conf/ipps/ZarandiMAP07 fatcat:emy5lftuqff7vd3yqavwkslnsi