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Constructing a Weak Memory Model
2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA)
Weak memory models are a consequence of the desire on part of architects to preserve all the uniprocessor optimizations while building a shared memory multiprocessor. The efforts to formalize weak memory models of ARM and POWER over the last decades are mostly empirical -- they try to capture empirically observed behaviors -- and end up providing no insight into the inherent nature of weak memory models. This paper takes a constructive approach to find a common base for weak memory models: wedoi:10.1109/isca.2018.00021 dblp:conf/isca/ZhangVWAA18 fatcat:5n5xvjz5dfhyhkt2u4evd3jssm