A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf
.
Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects
IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002.
As technology advances towards billion transistor systems, the cost of complex wire networks will require area efficient wiring methodologies. This paper explores the tradeoffs between wire latency, throughput and area for deep submicron (DSM) interconnect technologies. From basic physical models, optimal wiring sizing for repeater networks are rigorously derived and compared to HSPICE simulations. Key case studies from 25Onm to 70nm technologies reveal that significant wire orea reduction
doi:10.1109/iccad.2002.1167547
fatcat:i2lt6fpgybb7fcf4zid63t7are