Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects

H. Shah, P. Shin, B. Bell, M. Aldredge, N. Sopory, J. Davis
IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002.  
As technology advances towards billion transistor systems, the cost of complex wire networks will require area efficient wiring methodologies. This paper explores the tradeoffs between wire latency, throughput and area for deep submicron (DSM) interconnect technologies. From basic physical models, optimal wiring sizing for repeater networks are rigorously derived and compared to HSPICE simulations. Key case studies from 25Onm to 70nm technologies reveal that significant wire orea reduction
more » ... %) can be achieved with optimal wire sizing to maximize the throughput per unit wire area
doi:10.1109/iccad.2002.1167547 fatcat:i2lt6fpgybb7fcf4zid63t7are