This manuscript is a thorough study of FPGA implementation of Finite Impulse response (FIR) with low cost and high performance. The key observation of this paper is an elaborate analysis about hardware implementations of FIR filters using different algorithm i.e., Distributed Arithmetic (DA), DA-Offset Binary Coding (DA-OBC), Common Subexpression Elimination (CSE) and sum -of-power-oftwo (SOPOT) with less resources and without affecting the performance of the original FIR Filter.