Performance Modeling of Multithreaded Programs for Mobile Asymmetric Chip Multiprocessors

Ryan W. Moore, Bruce R. Childers, Jingling Xue
<span title="">2015</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="" style="color: black;">2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conference on Embedded Software and Systems</a> </i> &nbsp;
Asymmetric chip multiprocessors (ACMPs) have multiple core types that are instruction-set compatible but optimized differently to trade performance and power in mobile devices. The challenge for ACMPs is to map the program to the best core type and thread count to achieve performance requirements under power constraints. This paper describes an empirical strategy, MONARCH, to automatically build estimation models that capture how a multithreaded program's performance scales with thread count
more &raquo; ... core type. We show that MONARCH's models are accurate and useful to find mappings that achieve performance goals while minimizing power.
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="">doi:10.1109/hpcc-css-icess.2015.151</a> <a target="_blank" rel="external noopener" href="">dblp:conf/hpcc/MooreCX15</a> <a target="_blank" rel="external noopener" href="">fatcat:2mgx2e27tzh47aznfw4nvmfegq</a> </span>
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