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A runtime reconfigurable architecture for high speed Viterbi and Turbo decoding is designed and implemented on an FPGA. The architecture can be reconfigured to decode a range of convolutionally coded data with constraint lengths varying from 3 to 9, rates 1/2 and 1/3, and various generator polynomials. It can also be reconfigured to decode Turbo coded data with constraint length 4 and rate 1/3. Reconfiguration of the architecture requires a single clock cycle and does not require FPGAdoi:10.1109/icassp.2003.1202412 dblp:conf/icassp/CavallaroV03 fatcat:4ktz2r47cbairnxzjugklsnrvq