Viturbo: a reconfigurable architecture for Viterbi and turbo decoding

J.R. Cavallaro, M. Vaya
2003 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03).  
A runtime reconfigurable architecture for high speed Viterbi and Turbo decoding is designed and implemented on an FPGA. The architecture can be reconfigured to decode a range of convolutionally coded data with constraint lengths varying from 3 to 9, rates 1/2 and 1/3, and various generator polynomials. It can also be reconfigured to decode Turbo coded data with constraint length 4 and rate 1/3. Reconfiguration of the architecture requires a single clock cycle and does not require FPGA
more » ... uire FPGA reprogramming. The proposed architecture can deliver data rates up to 60.5 Mbps for Viterbi decoding and 3.54 Mbps for Turbo decoding, making it suitable for a range of wireless communication standards like IEEE 802.11a, 3GPP, GSM, GPRS, and many others.
doi:10.1109/icassp.2003.1202412 dblp:conf/icassp/CavallaroV03 fatcat:4ktz2r47cbairnxzjugklsnrvq