Code placement in hardware software Co synthesis to improve performance and reduce cost

S. Parameswaran
Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001  
This paper introduces an algorithm for code placement in cache, and maps it to memory using a second algorithm. The target architecture is a multiprocessor system with 1 st level cache and a common main memory. These algorithms guarantee that as many instruction codewords as possible of the high priority tasks remain in cache all of the time so that other tasks do not overwrite them. This method improves the overall performance, and might result in cheaper systems if more powerful processors
more » ... erful processors are not needed. Amount of memory increase necessary to facilitate this scheme is in the order of 13%. The average percentage of highest priority tasks always in memory can vary from 3% to 100% depending upon how many tasks (and their sizes) are allocated to each processor.
doi:10.1109/date.2001.915089 dblp:conf/date/Parameswaran01 fatcat:mwpe5bzsxff3rjgqfmmmlcr6em