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In all digital designs we are using the storage elements. Basic storage elements are the flip-flops, in this paper we focus on the low power flip-flop using pulse triggered structure based on signal feed through scheme. The proposed pulse triggered flip-flop solves the long discharging path in conventional designs and this design works with the low power and it shows the high performance. The proposed pulse triggered flip-flop simulation results testing in CMOS 90nm technology. The power andfatcat:iuxfu7mcxrfw5jvdk5s4ceqj4u