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Hardware architectures for successive cancellation decoding of polar codes
2011
2011 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)
The recently-discovered polar codes are widely seen as a major breakthrough in coding theory. These codes achieve the capacity of many important channels under successive cancellation decoding. Motivated by the rapid progress in the theory of polar codes, we propose a family of architectures for efficient hardware implementation of successive cancellation decoders. We show that such decoders can be implemented with O(n) processing elements and O(n) memory elements, while providing constant
doi:10.1109/icassp.2011.5946819
dblp:conf/icassp/LerouxTVG11
fatcat:nktpgmjsyfdfloq3lrw4ntm7ey