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Register files of microprocessors have often been cited as performance bottlenecks and significant consumers of energy. The robust and modular nature of quasi-delay insensitive (QDI) design offers a toolchest of techniques for improving average-case performance and reducing energy consumption of register files, which cannot be leveraged as easily in synchronous designs. In this paper, we focus on the design of an asynchronous register core, the heart of a register file. We describe the verticaldoi:10.1109/async.2004.1299289 dblp:conf/async/FangM04 fatcat:52l74bdzdfdjheh6ffa6crmmqe