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This paper describes a gate-level power minimization methodology using dual supply voltages. Gates and flip-flops off the critical paths are made to operate at the reduced supply voltage to save power. Core technologies are dual-V DD circuit synthesis and P&R. We give a brief overview on existing low-power EDA technologies as background and discuss advantages and challenges of the dual-VDD approach. Through real design examples, we will show that the approach reduces power effectively whiledoi:10.1145/368434.368590 dblp:conf/aspdac/UsamiI00 fatcat:6m3a3snj7vehtaetzosuekx3sy