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Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions
32nd International Symposium on Computer Architecture (ISCA'05)
Secure processors enable new applications by ensuring private and authentic program execution even in the face of physical attack. In this paper we present the AEGIS secure processor architecture, and evaluate its RTL implementation on FPGAs. By using Physical Random Functions, we propose a new way of reliably protecting and sharing secrets that is more secure than existing solutions based on non-volatile memory. Our architecture gives applications the flexibility of trusting and protecting
doi:10.1109/isca.2005.22
dblp:conf/isca/SuhOSD05
fatcat:xhedgrinvndhjfa4ejbgjzx35e