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This paper introduces a novel approach to efficiently implement several useful architectural features in asynchronous applicationspecific ICs (ASICs). These features include speculation, preemption, and eager evaluation, which have so far only been available on CPUs, and have not been adequately investigated for custom ASICs. For the efficient implementation of the new architectural features, a radically new approach inspired by Sproull's counterflow pipelines  is proposed. The key idea isdoi:10.1109/iccad.2006.320024 fatcat:7jh36c3rvvgkxgvbdk4bkvtaki