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Investigation of transient fault effects in synchronous and asynchronous Network on Chip router
2011
Journal of systems architecture
This paper presents comparison of transient fault effects in an asynchronous NoC router and a synchronous one. The experiment is based on simulation-based fault injection method to assess the fault-tolerant behavior of both architectures. The effort has been accomplished by employing fault injector signal (FIS) in asynchronous design and synchronous one. Different fault models such as Crosstalk, SEU, and SET have been applied in both architectures to evaluate their robustness. Glitch fault
doi:10.1016/j.sysarc.2010.10.003
fatcat:xmktb2c3bbfolist73r3oimdba