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Power-aware communication optimization for networks-on-chips with voltage scalable links
2004
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '04
Networks-on-Chip (NoC) is emerging as a practical development platform for future systems-on-chip products. We propose an energyefficient static algorithm which optimizes the energy consumption of task communications in NoCs with voltage scalable links. In order to find optimal link speeds, the proposed algorithm (based on a genetic formulation) globally explores the design space of NoCbased systems, including task assignment, tile mapping, routing path allocation, task scheduling and link
doi:10.1145/1016720.1016763
dblp:conf/codes/ShinK04
fatcat:l53tdohfe5dwbbyipp6xwpu6ya