Area, Delay and Power Analysis of Built in Self Repair Using 2-D Redundancy

Aman Kumar Sabnani, Balwinder Singh
2015 International Journal of VLSI Design & Communication Systems  
System on Chip comprises of programmable processor, different controller and memory. As chip size is decreasing memory density is increasing. These high density memories are susceptible to faults. To increase the yield and make device reliable, testing and self-repair are the important issues. To repair embedded memories in SOC, Built in self-repair techniques are used by firstly detecting, then locating and in the end repairing the memory. In this paper six BISR are designed using six
more » ... March algorithms as MBIST then compared altogether. Since power dissipation during testing operation is around twice the power dissipation during normal operational mode, thus low power BISR design is necessary considering the power constraints these days. Due to high switching activity chip can get overheated resulting in malfunction and damage. Power consumption is reduced by reducing the switching activity in the address line when writing and reading the memory during test.
doi:10.5121/vlsic.2015.6503 fatcat:yb6k5oy46jcpnhxzdrtlefpasq