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Area, Delay and Power Analysis of Built in Self Repair Using 2-D Redundancy
2015
International Journal of VLSI Design & Communication Systems
System on Chip comprises of programmable processor, different controller and memory. As chip size is decreasing memory density is increasing. These high density memories are susceptible to faults. To increase the yield and make device reliable, testing and self-repair are the important issues. To repair embedded memories in SOC, Built in self-repair techniques are used by firstly detecting, then locating and in the end repairing the memory. In this paper six BISR are designed using six
doi:10.5121/vlsic.2015.6503
fatcat:yb6k5oy46jcpnhxzdrtlefpasq