Digital Implementation of a Single Dynamical Node Reservoir Computer

Miquel L. Alomar, Miguel C. Soriano, Miguel Escalona-Moran, Vincent Canals, Ingo Fischer, Claudio R. Mirasso, Jose L. Rossello
2015 IEEE Transactions on Circuits and Systems - II - Express Briefs  
Minimal hardware implementations of machinelearning techniques have been attracting increasing interest over the last decades. In particular, field-programmable gate array (FPGA) implementations of neural networks (NNs) are among the most appealing ones, given the match between system requirements and FPGA properties, namely, parallelism and adaptation. Here, we present an FPGA implementation of a conceptually simplified version of a recurrent NN based on a single dynamical node subject to
more » ... ed feedback. We show that this configuration is capable of successfully performing simple real-time temporal pattern classification and chaotic time-series prediction. Index Terms-Artificial neural networks (ANNs), fieldprogrammable gate arrays (FPGAs), hardware (HW), multiple signal classification, neural network (NN), pattern recognition, recurrent neural networks (RNN), time-series prediction. 1549-7747
doi:10.1109/tcsii.2015.2458071 fatcat:loshr7xc3nbzzo7wqqoeuzy5cy