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Minimal hardware implementations of machinelearning techniques have been attracting increasing interest over the last decades. In particular, field-programmable gate array (FPGA) implementations of neural networks (NNs) are among the most appealing ones, given the match between system requirements and FPGA properties, namely, parallelism and adaptation. Here, we present an FPGA implementation of a conceptually simplified version of a recurrent NN based on a single dynamical node subject todoi:10.1109/tcsii.2015.2458071 fatcat:loshr7xc3nbzzo7wqqoeuzy5cy