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A 1 GS/s Continuous-time Delta-Sigma modulator (CT-∆ΣM) with 31 MHz bandwidth, 76.3 dB dynamic range and 72.5 dB signal-to-noise is reported in a 0.13 µm CMOS technology. The design employs an excess loop delay (ELD) of more than one clock cycle for achieving higher sampling rate. The ELD is compensated using a fast-loop formed around the last integrator by using a sample-and-hold. Further, the effect of this ELD compensation scheme on the signal transfer function (STF) of a feedforward CT-∆Σdoi:10.1109/mwscas.2012.6292142 dblp:conf/mwscas/BalagopalS12a fatcat:otjk3mcehjgqxpbqduiglkawo4