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Automatic incorporation of on-chip testability circuits
1990
Conference proceedings on 27th ACM/IEEE design automation conference - DAC '90
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This paper presents a system which automatically incorporates testability circuits into ECL chips. This system incorporates three types of circuit: (1) random access scan circuit, clock suppression circuit for delay fault testing, and (3) pin scanwut circuit for chip vo pin observation in board testing. Fanout destinations of each gate in the testability circuits are localized on a chip to keep the logicalnetlength within the limit. This system was used to develop the new Fujitsu VP-2000 supercomputer.
doi:10.1145/123186.123393
dblp:conf/dac/Ito90
fatcat:hulnutouzrgvfet5oxoijtr7vy