Fast error aware model for arithmetic and logic circuits

Samy Zaynoun, Muhammad S. Khairy, Ahmed M. Eltawil, Fadi J. Kurdahi, Amin Khajeh
<span title="">2012</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/nmhv25e6jvhplcow6e2chjryx4" style="color: black;">2012 IEEE 30th International Conference on Computer Design (ICCD)</a> </i> &nbsp;
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/iccd.2012.6378659">doi:10.1109/iccd.2012.6378659</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/iccd/ZaynounKEKK12.html">dblp:conf/iccd/ZaynounKEKK12</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/34jqi77j4fazfjuzrpjrecqyc4">fatcat:34jqi77j4fazfjuzrpjrecqyc4</a> </span>
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