A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is
PCI Express is a ubiquitous bus interface providing the highest bandwidth connection in the PC platform. Sadly, support for it in FPGAs is limited and/or expensive. The Speedy PCIe core addresses this problem by bridging the gap from the bare bones interface to a user friendly, high performance design. This paper describes some of the fundamental design challenges and how they were addressed as well as giving detailed results. The hardware and software source code are available for freedoi:10.1109/fpl.2012.6339270 dblp:conf/fpl/Bittner12 fatcat:zz6zyndd5zaaxnqryhhqlo2hci