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FIFO power optimization for on-chip networks
2004
Proceedins of the 14th ACM Great Lakes symposium on VLSI - GLSVLSI '04
As the design community moves towards architecting multiprocessor systems-on-chip (MPSoC), it is widely believed that an on-chip interconnection network is potentially the best candidate to satisfy the high aggregate throughput needed by dozens of IP blocks. In this context, power (energy) estimation and reduction techniques for switches and links, the core components of an interconnection network, gain added significance. FIFO buffers are a key component of a majority of network switches
doi:10.1145/988952.988998
dblp:conf/glvlsi/BanerjeeD04
fatcat:larhmk5jvzaodozt7ztvrfyzwa