Signal Integrity: Fault Modeling and Testing in High-Speed SoCs [chapter]

Mehrdad Nourani, Amir Attarha, Krishnendu Chakrabarty
2002 SOC (System-on-a-Chip) Testing for Plug and Play Test Automation  
As we approach 100nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-onchips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the high-speed interconnects. Then, we present a BIST-based test methodology that includes two special cells to detect
more » ... d measure noise and skew occurring on the interconnects of the gigahertz system-on-chips. Using an inexpensive test architecture the integrity information accumulated by these special cells can be scanned out for final test and reliability analysis.
doi:10.1007/978-1-4757-6527-4_12 fatcat:cxgzdzhu3becxlez7t2kjuvfwe