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Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
[chapter]
2002
SOC (System-on-a-Chip) Testing for Plug and Play Test Automation
As we approach 100nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-onchips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the high-speed interconnects. Then, we present a BIST-based test methodology that includes two special cells to detect
doi:10.1007/978-1-4757-6527-4_12
fatcat:cxgzdzhu3becxlez7t2kjuvfwe