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A Soft Processor Overlay with Tightly-coupled FPGA Accelerator
[article]
2016
arXiv
pre-print
FPGA overlays are commonly implemented as coarse-grained reconfigurable architectures with a goal to improve designers' productivity through balancing flexibility and ease of configuration of the underlying fabric. To truly facilitate full application acceleration, it is often necessary to also include a highly efficient processor that integrates and collaborates with the accelerators while maintaining the benefits of being implemented within the same overlay framework. This paper presents an
arXiv:1606.06483v1
fatcat:5vb7ne7yyverjbxc5i5isybgnu