A new binary arithmetic for finite-word-length linear controllers: MEMS applications

A. K. Oudjida, A. Liacha, M. L. Berrandjia, N. Chaillet
2014 2014 9th International Design and Test Symposium (IDT)  
This thesis addresses the problem of optimal hardware-realization of finite-word-length (FWL) linear controllers dedicated to MEMS applications. The biggest challenge is to ensure satisfactory control performances with a minimal hardware. To come up, two distinct but complementary optimizations can be undertaken: in control theory and in binary arithmetic. Only the latter is involved in this work. Because MEMS applications are targeted, the binary arithmetic must be fast enough to cope with the
more » ... rapid dynamic of MEMS; power-efficient for an embedded control; highly scalable for an easy adjustment of the control performances; and easily predictable to provide a precise idea on the required logic resources before the implementation. The exploration of a number of binary arithmetics showed that radix-2 r is the best candidate that fits the aforementioned requirements. It has been fully exploited to designing efficient multiplier cores, which are the real engine of the linear systems. The radix-2 r arithmetic was applied to the hardware integration of two FWL structures: a linear time variant PID controller and a linear time invariant LQG controller with a Kalman filter. Both controllers showed a clear superiority over their existing counterparts, or in comparison to their initial forms. iv Glossary Abstraction Simplification of details, approximation of complex problems ADC Analog to Digital Converter AFM Atomic Force Microscopy ALU Arithmetic and Logic Unit ASIC Application Specific Integration Circuit Ath Adder Depth, the maximum number of serial adder-operations from input to output Avg Average number of additions BHM Bull Horrocks modified, an existing heuristic MCM algorithm BIGE Bounded Inverse Graph Enumeration, an optimal SCM algorithm BMA Booth Multiplication Algorithm, an existing algorithm for signed multiplication CAD Computer-aided design, tools for design automation CDE Common Digit Elimination CLB Configurable Logic Bloc CMOS Complementary Metal Oxide Semiconductor COTS Commercial Off-The-Shelf CSD Canonical Signed Digit, the SD form with no adjacent nonzero digits and the minimum number of nonzero digits CSE Common Subexpression Elimination, a framework for solving SCM and MCM DAC Digital to Analog Converter DAG Directed Acyclic Graphs, a framework for solving SCM and MCM DBNS Double Base Number System, an existing number representation system DFS Dynamic Frequency Scaling Digit Clashing The CSE problem of disappearing patterns due to colliding digits DMAC Double Multiply-And-Accumulate DSP Digital-Signal-Processor/Processing FF Flip-Flop FPGA Field Programmable Gate Array FPR Fixed-Point Representation FWL Finite Word Length H(k) Heuristic with k extra nonzero digits, an existing heuristic SCM algorithm H(k)+ODP The H(k) algorithm with ODPs, a proposed heuristic SCM algorithm Hcub Cumulative Benefit Heuristic, an existing MCM algorithm v HDL Hardware Description Language Heuristic An effective but potentially suboptimal method for solving a problem HIS Host Side Interface HPM High Performance Multiplication, an existing adder reduction technique IOB Input Output Block Logic resources An abstraction of the amount of silicon required to implement a logic function LQG Linear Quadratic Gaussian LTI Linear Time Invariant LTV Linear Time Variant MAC Multiply-And-Accumulate MAG Minimized Adder Graph, an existing optimal SCM algorithm MBMA Modified Booth Multiplication Algorithm, , an existing algorithm for signed multiplication MCM Multiple Constant Multiplication, find a low-cost add-shift-subtract realization of multiplication by each of the given constants MEMS Micro-Electro-Mechanical Structure MM Matrix Multiplication MPC Model Predictive Control MPM Multi-Precision Multiplication MSD Minimal Signed Digit, any SD representation with the minimum number of nonzero digits MV Multiplication by a Variable NEMS Nano-Electro-Mechanical Structure NP-hard Non-deterministic Polynomial-time hard ODMAC Optimized Double Multiply-And-Accumulate
doi:10.1109/idt.2014.7038608 dblp:conf/idt/OudjidaLBC14 fatcat:ykr7hhrd7ndy5jbmu53hb3t7vm