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Exploiting Operand Availability for Efficient Simultaneous Multithreading
IEEE transactions on computers
We propose several schemes to improve the scalability, reduce the complexity and delays, and increase the throughput of dynamic scheduling in SMT processors. Our first design is an adaptation of the recently proposed instruction packing to SMT. Instruction packing opportunistically packs two instructions (possibly from different threads), each with at most one nonready source operand at the time of dispatch, into the same issue queue entry. Our second design, termed 2OP_BLOCK, takes these ideasdoi:10.1109/tc.2007.28 fatcat:3vuvqhd3pfggvmnrihjb6m6i7a