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This paper is the first to combine the joint module-selection and retiming problem with the use of carry-save representation in the optimization of a synchronous circuit. To solve this problem efficiently, we first create a mixed-representation data-flow graph (MFG) by inserting signal representation conversion vertices into the data-flow graph, thus allowing carry-save representation to be freely selected for use. We then identify key properties of an optimal implementation of the MFG thatdoi:10.1109/tcad.2003.814251 fatcat:3vlyjs2s45cwtdrbazjwh5geja