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Multiplier-Less Based Parallel-Pipelined FFT Architectures for Wireless Communication Applications
Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005.
This paper proposes two novel parallel-pipelined FFT architectures based on multiplier-less implementation targeting wireless communication applications, such as IEEE 802.11 wireless baseband chip and MC-CDMA receiver. The proposed parallelpipelined architectures have the advantages of high throughput and high power efficiency. The multiplier-less architecture uses shift and addition operations to realize complex multiplications. By combining a new commutator architecture, and a low powerdoi:10.1109/icassp.2005.1416236 dblp:conf/icassp/HanAEH05 fatcat:klqpnt66tngixfjygenbtl5aey