Design of a family of VLSI high speed fuzzy processors

A. Gabrielli, E. Gandolfi, M. Masetti
Proceedings of IEEE 5th International Fuzzy Systems  
This paper describes the architecture of two VLSI Fuzzy chips designed to run at very high speed: 50 Mega Fuzzy Inference per Second (MFIPS) at least. The two projects differ in the number of inputs; one processes 2 -4 seven bit inputs while the other one 8 -16 seven bit inputs. The two chips have been designed for applications in High Energy Physics Experiments (HEPE) where the apparatus, called trigger device, needs to discriminate different nuclear events in few microseconds. So far most of
more » ... he fuzzy logic applications do not require high speed because not required by the industrial applications, therefore they have been done by implementing the fuzzy system on microprocessors, DSPs, or on commercial fuzzy chips which do not have very high speed performances like those necessary for HEPE. In the first phase of our research 1.0 ym VLSI fuzzy chip [ 11, [2] prototype with four 7 bit inputs and one output running at 50 MFIPS was designed and constructed whose processing rate depends upon the number of rules of the fuzzy system. To further increase the speed we have faced the problem of processing, when possible, only the active fuzzy rules which are a few percent of the total ones. The research carried out on this prototype allowed us to extract some general conclusions: for applications with no more than 4 inputs only the active rules are processed. Our design has a processing rate of 320 ns for 4 inputs, whichever is the fuzzy system. The processing rate is higher if less than 4 inputs are processed and reaches 100 ns for two inputs. for applications which need 8 -16 inputs an Active Rule Selector (ARS) has been designed to increase the processing speed which is 20 ns times the number of processed rules. The ARS is able to reject most of the non active rules. This paper starts with a concise description of the design of the first chip, already constructed and running, then describes in more details the two new projects which are designed in 0.7 ym CMOS technology with ES2 foundry standard cells.
doi:10.1109/fuzzy.1996.552332 fatcat:clpwyiumejayrexa32d2i4cuai