FPGA Based Architectures for H. 264/AVC Video Compression Standard

Luciano Agostini, Sergio Bampi
2006 2006 International Conference on Field Programmable Logic and Applications  
This paper presents the architecture and the VHDL design of the integer Two-Dimensional Discrete Cosine Transform (2-D DCT) used in the H.264/AVC codecs. The forward and inverse 2-D DCT architectures were designed and their synthesis results mapped to Altera FPGAs are presented. The 2-D DCT calculation is performed by exploring the separability property, in such way, each 2-D DCT architecture is divided in two 1-D DCT calculations that are joined through a transpose buffer. The 1-D DCT
more » ... s implemented and herein described are multiplierless, hence optimized shift-add operations are used. The architectures have a dedicated pipeline, optimized to process one input data per clock cycle. These architectures are able to cope with H.264/AVC encoder or decoder requirements targeting High Definition Digital Television (HDTV), with 1920x1080 pixel/frame at 30 frames per second. Keywords −− H.264/AVC video compression, dedicated hardware for video compression, 2-D FDCT, 2-D IDCT, integer transforms.
doi:10.1109/fpl.2006.311361 dblp:conf/fpl/AgostiniB06 fatcat:ikeee2a6f5bqdobe7mgcb2rba4