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FPGA Based Architectures for H. 264/AVC Video Compression Standard
2006
2006 International Conference on Field Programmable Logic and Applications
This paper presents the architecture and the VHDL design of the integer Two-Dimensional Discrete Cosine Transform (2-D DCT) used in the H.264/AVC codecs. The forward and inverse 2-D DCT architectures were designed and their synthesis results mapped to Altera FPGAs are presented. The 2-D DCT calculation is performed by exploring the separability property, in such way, each 2-D DCT architecture is divided in two 1-D DCT calculations that are joined through a transpose buffer. The 1-D DCT
doi:10.1109/fpl.2006.311361
dblp:conf/fpl/AgostiniB06
fatcat:ikeee2a6f5bqdobe7mgcb2rba4