Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits

Ming-Dou KER, Yuan-Wen HSIAO
2009 IEICE transactions on electronics  
An impedance-isolation technique is proposed for on-chip ESD protection design for radio-frequency (RF) integrated circuits (ICs), which has been successfully verified in a 0.25-μm CMOS process with thick top-layer metal. With the resonance of LC-tank at the operating frequency of the RF circuit, the impedance (especially, the parasitic capacitance) of the ESD protection devices can be isolated from the RF input node of low-noise amplifier (LNA). Therefore, the LNA can be codesigned with the
more » ... posed impedance-isolation technique to simultaneously achieve excellent RF performance and high ESD robustness. The power gain (S 21 -parameter) and noise figure of the ESD protection circuits with the proposed impedance-isolation technique have been experimentally measured and compared to those with the conventional double-diodes ESD protection scheme. The proposed impedance-isolation technique had been demonstrated to be suitable for on-chip ESD protection design for RF ICs. key words: electrostatic discharge (ESD), impedance-isolation technique, LC-tank, noise figure power gain
doi:10.1587/transele.e92.c.341 fatcat:2goxy357ejfytchfs76yoz2wdq