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Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits
2009
IEICE transactions on electronics
An impedance-isolation technique is proposed for on-chip ESD protection design for radio-frequency (RF) integrated circuits (ICs), which has been successfully verified in a 0.25-μm CMOS process with thick top-layer metal. With the resonance of LC-tank at the operating frequency of the RF circuit, the impedance (especially, the parasitic capacitance) of the ESD protection devices can be isolated from the RF input node of low-noise amplifier (LNA). Therefore, the LNA can be codesigned with the
doi:10.1587/transele.e92.c.341
fatcat:2goxy357ejfytchfs76yoz2wdq