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A Hierarchical Architectural Framework for Reconfigurable Logic Computing
2013
2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum
Recently there has been growing interest in using Reconfigurable Logic (RL) for computation because of the significant performance gains that they can provide over traditional architectures on many classes of workloads. While there is a rich body of prior work proposing a variety of reconfigurable systems, we believe there hasn't been an attempt to clearly identify the architectural tradeoff spaces for an RL compute engine and to clearly separate architectural choices from implementation ones.
doi:10.1109/ipdpsw.2013.252
dblp:conf/ipps/LiPPWE13
fatcat:iznf6jppmzffba6bd6g5mn32sa