Analysis of blocking dynamic circuits

T. Thorp, D. Liu, P. Trivedi
<span title="">2003</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/uqbr2omxsbdgtaxslmblka2nnu" style="color: black;">IEEE Transactions on Very Large Scale Integration (vlsi) Systems</a> </i> &nbsp;
In order for dynamic circuits to operate correctly, their inputs must be monotonically rising during evaluation. Blocking dynamic circuits satisfy this constraint by delaying evaluation until all inputs have been properly setup relative to the evaluation clock. By viewing dynamic gates as latches, we demonstrate that the optimal delay of a blocking dynamic gate may occur when the setup time is negative. With blocking dynamic circuits, cascading low-skew dynamic gates allows each dynamic gate to
more &raquo; ... tolerate a degraded input level. The larger noise margin provides greater flexibility with the delay versus noise margin tradeoff (i.e., the circuit robustness versus speed tradeoff). This paper generalizes blocking dynamic circuits and provides a systematic approach for assigning clock phases, given delay and noise margin constraints. Using this framework, one can analyze any logic network consisting of blocking dynamic circuits.
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tvlsi.2003.816140">doi:10.1109/tvlsi.2003.816140</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/ged3ovvjyrgnrookgjwcz3d7ai">fatcat:ged3ovvjyrgnrookgjwcz3d7ai</a> </span>
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