SET and RESET Pulse Characterization in BJT-Selected Phase-Change Memories

F. Bedeschi, E. Bonizzoni, G. Casagrande, R. Gastaldi, C. Resta, G. Torelli, D. Zella
2005 IEEE International Symposium on Circuits and Systems  
This paper presents program pulse characterization in an 8-Mb BJT-selected Phase-Change Memory test chip. Experimental results of the impact of the bit-line resistance over programming pulses efficiency are provided. Furthermore, in order to compensate for spreads in cell physical parameters in an array portion, a non-conventional staircase-down program pulse is proposed and experimentally evaluated. 0-7803-8834-8/05/$20.00 ©2005 IEEE.
doi:10.1109/iscas.2005.1464826 dblp:conf/iscas/BedeschiBCGRTZ05 fatcat:2xwfg3gaxjd77cotywk3mn2xfu