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Circuit implementation of a 600 MHz superscalar RISC microprocessor
Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273)
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The circuit techniques used to implement a 600MHz, out-of-order, superscalar RISC Alpha microprocessor are described. Innovative logic and circuit design created a chip that attains 30+ SpecInt95 and 50+ SpecFP95, and supports a secondary cache bandwidth of 6.4GB/s. Microarchitectural techniques were used to optimize latencies and cycle time, while a variety of static and dynamic design methods balanced critical path delays against power consumption. The chip relies heavily on full custom
doi:10.1109/iccd.1998.727030
dblp:conf/iccd/MatsonBBBBCFGPW98
fatcat:vrxyh73tpfayncd23n6j2tawxi